This invention is in the field of integrated circuits. Embodiments are more specifically directed to isolator structures in integrated circuits.
As well known in the art, some implementations of modern integrated circuits require the communication of signals between integrated circuits that are not referenced to the same ground voltage, either (or both) in the DC and AC sense. In those implementations, the direct coupling of input/output terminals could result in a significant voltage differential between the respective ground levels. In some applications, this ground voltage differential can be as high as hundreds or thousands of volts, sufficient to damage the integrated circuits and cause system failure. Similarly, transient high voltage spikes at one of the integrated circuits can couple via the connected input/output terminals to other integrated circuits. For example, a typical voltage spike at a high voltage motor can couple from a motor controller device at the motor to an integrated circuit at a human interface device (e.g., keypad); such spikes can cause damage and, in the case of a human interface device, can affect the human user.
Isolator structures are commonly implemented into integrated circuits intended for these applications, with those structures deployed at the input/output terminals. These isolator structures are typically in the form of capacitors or inductors. For the example of an isolator constructed as a capacitor, the capacitor is inserted in series between the terminal or pad and the internal circuit. The goal of these isolator structures 5 is to absorb the voltage differential between ground levels (or the transient spike) with minimum attenuation of signal information.
FIG. 1a illustrates, in cross-section, the construction of a conventional isolator structure in the form of high voltage capacitor 7 deployed in an integrated circuit. In this arrangement, capacitor 7 is a parallel-plate capacitor in which upper plate 8a and lower plate 8b are formed in separate metal levels. In this example, capacitor 7 is deployed directly at an external terminal (e.g., an input) of the integrated circuit, as evident by wire bond 5 attached to the bond pad (exposed through protective overcoat 9 and top dielectric layer 10h) that serves as exposed upper plate 8a. In this conventional example, integrated circuit 4 is fabricated to have seven levels of metal conductors, with lower plate 8b formed in the second metal level and upper plate 8a formed in the seventh (topmost) metal level. Accordingly, the intervening dielectric between upper and lower plates 8a, 8b includes five layers 10c through 10g of interlevel dielectric material (e.g., silicon dioxide); two interlevel dielectric layers 10a, 10b underlie lower plate 8b, separating it from substrate 11 and isolation dielectric structure 12. Each of interlevel dielectric layers 10 serves to insulate adjacent levels of metallization in the vertical direction in the cross-section of FIG. 1a. As such, interlevel dielectric layers 10c through 10g between upper and lower plates 8a, 8b are formed between the formation and patterned etch of each of the intervening metal levels that form conductors elsewhere in the integrated circuit. The relatively large cumulative thickness of interlevel dielectric layers 10c through 10g results in capacitor 7 being capable of withstanding and absorbing relatively high voltages.
In addition to capacitor 7 formed between upper and lower plates 8a, 8b, a parasitic capacitor is defined by the structure shown in FIG. 1a. Specifically, parasitic parallel-plate capacitor 7p is present between lower plate 8a and substrate 11 disposed under lower plate 8b, with the capacitor dielectric formed of interlevel dielectric layers 10a, 10b, and isolation oxide structure 12 beneath interlevel dielectric layer 10a. Isolation oxide structure 12 is a conventional dielectric structure formed into substrate 11, typically with the purpose of isolating adjacent transistors formed at the surface of substrate 11 from one another; isolation oxide structure 12 may be formed by thermal oxidation (e.g., the well-known LOCOS process) or as shallow trench isolation. Because the cumulative thickness of interlevel dielectric layers 10a, 10b, and isolation oxide structure 12 can be substantially less than that of interlevel dielectric layers 10c through 10g, parasitic capacitor 7p can present a significantly larger capacitance than does high voltage capacitor 7.
The electrical effect of parasitic capacitor 7p is illustrated in FIG. 1b. High voltage capacitor 7 couples terminal 5 of the integrated circuit (i.e., wire bond 5 of FIG. 1a) to internal node 13, which is typically coupled to the internal functional circuitry of the integrated circuit. However, parasitic capacitor 7p also couples input 5 to a fixed voltage level, for example the substrate voltage Vsub at substrate 11 of the integrated circuit (e.g., a ground level), which can cause attenuation of the signal level received at input 5 from that reaching internal node 13. In an example in which high voltage capacitor 7 has a cumulative dielectric thickness (i.e., of interlevel dielectric layers 10c through 10g cumulatively) of 12.7 μm between upper and lower plates 8a, 8b, and parasitic capacitor 7p has a cumulative dielectric thickness (i.e., interlevel dielectric layers 10a and 10b and isolation dielectric structure 12 cumulatively) of 2.8 μm between lower plate 8b and substrate 11, parasitic capacitor 7p may present a capacitance more than ten times that of high voltage capacitor 7 (e.g., 400 fF vs. 30 fF). Fundamental circuit analysis shows that parasitic capacitor 7p results in the signal level at internal node 13 being only about 10 percent of the magnitude of that received at input 5.
By way of further background, another conventional isolator structure is constructed similarly as capacitor 7 of FIG. 1a, but includes a doped well underlying the bottom plate. With reference to the structure of FIG. 1a, this structure would have such a doped well in place of isolation dielectric structure 12 (albeit at a shallower depth), with the doping of that well opposite to that of substrate 11 (e.g., an n-well formed into p-type substrate 11).
In either of these conventional structures, conventional approaches to reducing the capacitance of parasitic capacitor 7p have been problematic. For example, forming lower plate 8b in a higher level of metal would increase the dielectric thickness between lower plate 8b and substrate 11, reducing its capacitance. However, this would also have the effect of reducing the dielectric thickness between lower plate 8b and upper plate 8a, as the dielectric of capacitor 7 would be thinner (i.e., fewer interlevel dielectric layers 10 between the plates). This reduced dielectric thickness would, in turn, reduce the high voltage isolation capability of capacitor 7. Another approach would be to form both lower plate 8b and upper plate 8a in higher levels of metal, to increase the dielectric thickness between lower plate 8b and substrate 11 while maintaining the same dielectric thickness for capacitor 7. However, as evident from FIG. 1a, upper plate 8a may already be constructed in the highest metal level in the integrated circuit; accordingly, this approach could require increasing the number of metal conductor levels from what it otherwise would be, which increases the manufacturing cost of the integrated circuit.
As mentioned above, integrated inductors are also used as isolator structures, for example in the form of an isolating transformer. Conventional inductive isolator structures are similar to that shown in FIG. 1a, except that, instead of a parallel plate structure, the two metal conductor levels are patterned as a pair of overlying coils of sufficient length to define the desired inductance and coupling to one another. However, a parasitic capacitance similar to that shown as parasitic capacitor 7p would be presented between the lower coil and the underlying substrate. This parasitic capacitor can similarly attenuate the signal magnitude communicated through the isolator structure, as discussed above.